The Most Complete Collection of Fast Instruction Set Simulators for RISC-V in the Industry

If you are developing software for a RISC-V processor, core, or system where you do not have access to the hardware – then you probably need to have a look at using a simulator to develop your software on. Reasons for not having access to the hardware are many. The most common being that the hardware is not yet designed or built and if this is a new chip then the use of a software model or ISS to get the software development started is essential.

With modern instruction sets and processor architectures it is essential that the code you develop is cross compiled and executed on the correct instruction set. Use of host x86 execution only goes so far for modern embedded processors. Many current embedded processors have DSP instructions or specific architectural instructions that affect CPU operation and these just will not exist in a different host processor. Also maybe you have a binary library of say an ARM or MIPS audio or video codec. This will just not run on an x86 and requires you run it on the correct Instruction Set Architecture (ISA). So running your code on the correct ISA is becoming more and more important to get started with early embedded software development.

An Instruction Set Simulator, or ISS, is often the first simulation product used in an embedded software development project. An ISS allows the development and debug of code for the target architecture on an x86/x64 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.

ISS Overview

Where can a RISC-V ISS be used in embedded software development?

A RISC-V ISS can be used by many different developers in different software development roles. Used by application software engineers who need to create software binaries on the latest architectures but who do not need platform components – a RISC-V ISS can work with a standard debuggers and GUIs which makes it very easy to get started with full source code interactive debugging.

Middleware library developers can also use a RISC-V ISS when building software libraries for common functions, for example multimedia standards where they code at the assembly level and make extensive use of the processor data path – a debugger/GUI shows detailed assembly and all processor registers.

Test engineers can use a RISC-V ISS in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.

A key component of a RISC-V ISS is the detailed RISC-V CPU models it uses

The Imperas ISS makes use of the Imperas OVP Fast Processor Model library providing access to almost 200 different instruction accurate embedded CPU model variants from the Imagination/MIPS 24Kc to the ARM Cortex-A72MPx4 quad core 64 bit processor, through to the RISC-V RV32G and RV64G. The Imperas ISS product package comes with all these CPU models and example usage of them.

This site, risc-v-development-environment.com, ‘Developing RISC-V based systems using the Imperas Software Development Environment’, ‘Using the Imperas software development environment for RISC-V based designs’, lists the many Fast Processor Models that are availble for RISC-V and other processor families.

With a modern ISS, speeds of up to 1,000 MIPS can be expected on modern desktop PCs.

Features of the Imperas RISC-V Instruction Set Simulator (ISS)

The Imperas RISC-V ISS is a program executable that is released to run in x86 32 bit Windows/Linux and x64 64 bit Windows/Linux environments.

There are command line arguments that select which processor family and specific processor variant, and which cross compiled application binary are to run.

The RISC-V ISS implements semi-hosting so that if your C program makes calls to standard newlib functions such as fopen, printf etc, then you need to just compile up your main.c and load it. The RISC-V ISS semi-hosting intercepts these newlib calls and implements them directly on the host making your cross-compiled application interact directly with the host PC.

Features:

  • includes the full library of all publicly released Imperas OVP Fast Processor Models
  • includes a GDB debugger for each CPU family
  • includes the Imperas Graphical User Interface (iGui) to provide full source code debug
  • configurable trace subsystem to provide instruction and register tracing
  • loads .elf file binaries directly
  • allows one instance of a single or multi-core CPU with full memory construction
  • uses built in semi-hosting to support library functions such as printf and fopen, and can access host native resources
  • can be run interactively or in script/batch mode for regression testing
  • includes Imperas Just-In-Time (JIT) Code Morphing high performance CPU simulator technology
  • works with Eclipse/CDT GUI

The Imperas RISC-V Instruction Set Simulator (ISS) includes a GUI and debugger

IGUI Overview

 An Example run of the Imperas Instruction Set Simulator (ISS)

ISS Run

Easy to use – watch a tutorial video (requires login)

To see a video tutorial of the use of the ISS, click the image:

ISS Tutorial Video

If you want to see other videos, OVP has a collection to view here.


Currently available Fast Processor Model Families.

FamilyModel Variant
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 I6500 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A32MPx1 Cortex-A32MPx2 Cortex-A32MPx3 Cortex-A32MPx4 Cortex-A35MPx1 Cortex-A35MPx2 Cortex-A35MPx3 Cortex-A35MPx4 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A55MPx1 Cortex-A55MPx2 Cortex-A55MPx3 Cortex-A55MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 Cortex-A73MPx1 Cortex-A73MPx2 Cortex-A73MPx3 Cortex-A73MPx4 Cortex-A75MPx1 Cortex-A75MPx2 Cortex-A75MPx3 Cortex-A75MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
RISC-V Models    RISC-V Models aliases RV32I RV32IM RV32IMC RV32IMAC RV32G RV32GC RV32GCN RV32E RV32EC RV64I RV64IM RV64IMC RV64IMAC RV64G RV64GC RV64GCN (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Andes_N25 Andes_NX25 Microsemi_CoreRISCV Microsemi_MiV_RV32IMA SiFive_E31 SiFive_E51 SiFive_U54 Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)